Chopsticks&Audiotracks

Recently I’ve been staying longer at campus to do reports.  There’s one big report which can’t be done at home as it needs a simulation software I can’t download at home for obvious reason. Expensive.  If I can’t get it legally, I usually tried torrent as the other resort (not necessarily the last), but not many people seem to use Cadence Virtuoso Verilog simulator at home.  Virtuoso is a verilog simulator used by many IC designers at some, if not most, companies.  It is also the simulator created by the owner of verilog HDL (Hardware Descriptive Language), Cadence.  No wonder the license price is out of student budgets.

However, there is this free verilog simulator that is widely used at home by students or just hobbyist.  It’s called Icarus Verilog. I actually downloaded this simulator a while ago, but I didn’t have the courage to try it since I haven’t really grasped the language’s concept so much.  The result, I kept using virtuoso provided by campus in VLSI lab linux box.  The lab’s atmosphere isn’t really comfortable, it gets really hot when the AC isn’t running, but gets real freezing if the AC is on.

Today, I dropped by the lab, tried some simulation -which didn’t go quite well- and learned quite verilog.  So after I got home, I tried the free Icarus simulator, and luckily I managed to write a small program on it.  I tried making multiplexer like this :

module mux(a, b, sel, y);
input [2:0] a;
input [2:0] b;
input sel;
output [2:0] y;

assign y = (sel) ? a : b;
endmodule

I saved it under mux.v, and created a testbench, mux_tb.v :

module mux_tb;
reg [2:0] a;
reg [2:0] b;
reg sel;

wire [2:0] y;

mux MUX0 (.a(a), .b(b), .sel(sel), .y(y));

initial begin
a = 3′b011;
b = 3′b110;
#40 sel = 1;
#40 sel = 0;
#40 sel = 1;
end

initial begin
$dumpfile (“mux.vcd”);
$dumpvars;
end

initial begin
$display(“\t\ta \tb \tsel \ty”);
$monitor(“\t\t%b \t%b \t%d \t%b”, a, b, sel, y);
end

initial
#500 $finish;
endmodule

It’s a simple 2 to 1 multiplexer with a and b as input, sel as selector and y as output.  I initialized the value of a and b randomly,  a = 011, b = 110.  The value of y will change according to the selector.  When sel=1 the value of y equals the value of a, otherwise y equals the value of b.  To make it interesting, I set the selector value to change every 40 nanoseconds (note that #40 means period in nanoseconds), this is to see the waveform changes as the selector change.  Icarus verilog is run on the terminal as a shell program.  To make it run, first I compile the codes, like compiling c codes via gcc, I typed this on terminal window :

$ iverilog -o mux_tb mux_tb.v mux.v

this will create executable mux_tb which is then run on simulation with vvp command :

$ vvp mux_tb

VCD info: dumpfile mux.vcd opened for output.

a        b     sel     y

011  110   x    x1x

011  110   1    011

011  110   0    110

011  110   1    011

sorry about the size